Senior Design Verification Engineer

Role summary

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The Senior Design Verification Engineer is expected to plan, develop and execute verification strategies for complex electronic or semiconductor designs. Responsibilities typically include creating verification plans, developing testbenches and automated test environments, writing and reviewing test cases, analysing simulation results, identifying design defects and supporting debugging through to resolution. Candidates should have strong experience with digital design verification, simulation tools and hardware description languages such as SystemVerilog or Verilog, along with familiarity with methodologies such as UVM. Experience in coverage-driven verification, regression management and technical documentation is valuable. Capgemini would expect strong problem-solving, communication and teamwork skills, with the ability to work independently and support junior engineers.

About the employer

Capgemini is a global technology and consulting company headquartered in France, serving clients across consulting, digital transformation, engineering, cloud, data, artificial intelligence and managed services. The company works with organisations in industries including financial services, manufacturing, automotive, telecommunications, healthcare, retail and the public sector. Capgemini helps clients modernise technology platforms, improve business processes and develop digital products. Its engineering teams may support embedded systems, electronics, software, product development and industrial technology programmes. In Malaysia, Capgemini operates as part of its wider Asia-Pacific delivery and consulting network, offering opportunities to work with international clients and distributed teams. The organisation generally values technical expertise, continuous learning, collaboration, professional certifications and the ability to deliver reliable solutions in complex client environments.