Senior RTL Engineer

Role summary

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A Senior RTL Engineer designs, develops and verifies digital hardware using Verilog or SystemVerilog, with responsibility for translating specifications into reliable, synthesizable RTL. Typical requirements include a degree in electrical or electronic engineering, strong digital-design fundamentals, experience with ASIC or FPGA development, and familiarity with simulation, synthesis, timing analysis and verification tools. Knowledge of coding standards, design-for-test, clock-domain crossing and low-power techniques is valuable. The candidate is expected to lead technical work, review designs, investigate complex issues, document solutions and collaborate with verification, physical-design and systems teams. Clear communication, independent problem-solving and the ability to meet quality and delivery targets are essential.

About the employer

Capgemini is a global business and technology transformation company headquartered in France. It provides consulting, technology services, engineering, cloud, data, artificial intelligence, cybersecurity and managed services to organizations across many industries. The company works with clients to modernize technology environments, build digital products, improve operations and adopt emerging technologies. Capgemini has a large international workforce and operates through a combination of consulting expertise, engineering capability and strategic partnerships with major technology providers. Its Malaysian operations support regional and global delivery, offering opportunities across software engineering, enterprise platforms, infrastructure, data, business transformation and technical consulting. Roles may involve multinational teams, structured delivery methods and continuous professional development. Specific responsibilities and compensation can vary considerably by business unit, project, experience level and the precise position advertised.