Middle RTL Engineer (Ukraine)

Role summary

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The Middle RTL Engineer role requires a candidate with a strong background in digital design and RTL coding, preferably with a degree in Electrical Engineering or a related field. The candidate should have experience with Verilog or VHDL, and familiarity with FPGA or ASIC design flows. Expectations include developing and optimizing RTL code, collaborating with cross-functional teams, and ensuring design meets performance and quality standards.

About the employer

Capgemini is a global leader in consulting, technology services, and digital transformation. With a strong heritage of over 50 years, Capgemini is at the forefront of innovation to address the entire breadth of clients’ opportunities in the evolving world of cloud, digital, and platforms. The company is driven by the conviction that the business value of technology comes from and through people. It is a multicultural company of over 270,000 team members in almost 50 countries.